`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2020/08/10 18:38:39
// Design Name: 
// Module Name: led_bling
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module led_bling(
    input           clk,
    input           rst,
    input   [3:0]   ena,
    output  [3:0]   led
    
);
 
 reg	[25:0]     time_cnt;   
    
 always @(posedge clk)begin
    if(rst)
        time_cnt <= 0;
    else
        time_cnt <= time_cnt + 1;   
 end   
    
assign led[0] = time_cnt[25] & ena[0];
assign led[1] = time_cnt[24] & ena[1];
assign led[2] = time_cnt[23] & ena[2];
assign led[3] = time_cnt[22] & ena[3];    
    
endmodule
